The present invention relates to a method of generating a clock and a semiconductor device.
In a communication system such as a wireless communication system, when a whole communication system is operated, a clock signal (a data rate clock) having a frequency is supplied to each component of the communication system according to a processing speed (a data rate) of a data signal of each component. Accordingly, in the communication system, it is necessary to generate the data rate clocks having various frequencies. To this end, the clock source is configured to generate a master clock having an accurately stabilized oscillation frequency, and the frequency of the master clock is divided to generate the data rate clocks having various frequencies, in consideration of simplification of a clock source of the data rate clock, synchronization of the whole communication system, and the like.
As an example of a conventional technique for dividing the frequency of the clock, there has been a method of dividing a frequency (an integer number frequency division method) with a frequency division ratio of an integer number (a frequency division integer number).
FIG. 4 is a block diagram showing a configuration of a conventional clock generating circuit 200 using the integer number frequency division method. FIG. 5 is a block diagram showing a clock frequency dividing circuit 50 of the conventional clock generating circuit 200. FIG. 6 is a time chart showing signals of the conventional clock generating circuit 200. It should be noted that, as an example of the conventional technique, the conventional clock generating circuit 200 performs an oversampling operation on the data rate with an oversampling rate k.
As shown in FIG. 4, the conventional clock generating circuit 200 (a frequency dividing circuit using the integer number frequency division method) includes the clock frequency dividing circuit 50; a data rate clock generating circuit 51; and a frequency division integer number (N) storage register 52. It should be noted that the frequency division integer number (N) storage register 52 stores a frequency division integer number (N).
In the conventional clock generating circuit 200, the clock frequency dividing circuit 50 is configured to receive a master clock S50, and to divide a frequency of the master clock S50 to generate a frequency divided clock S51. The data rate clock generating circuit 51 is configured to receive the frequency divided clock S51, and to further divide a frequency of the frequency divided clock S51 with the oversampling rate k to generate and output a data rate clock S53.
As shown in FIG. 5, the clock frequency dividing circuit 50 of the conventional clock generating circuit 200 includes a clock frequency dividing counter 53; a comparing unit 54; and a gate circuit 55.
In the clock frequency dividing circuit 50 of the conventional clock generating circuit 200, the clock frequency dividing counter 53 is configured to perform count up on the master clock S50 as an operation clock to output a counted-up value. The comparing unit 54 is configured to compare the counted-up value with a signal S52 indicating the frequency division integer number (N) retrieved from the frequency division integer number (N) storage register 52. When the counted-up value reaches the frequency division integer number (N), the comparing unit 54 is reset.
As shown in FIG. 6, a wave chart (a) represents an operation wave form of a clock frequency division counter value S54 as an output signal of the clock frequency dividing counter 53.
In the clock frequency dividing circuit 50, the gate circuit 55 is configured to calculate a logic product of an output S55 of the comparing unit 54 and the master clock S50, so that the gate circuit 55 generates the frequency divided clock S51. As shown in FIG. 6, a wave chart (b) represents the frequency divided clock S51.
In the conventional clock generating circuit 200, the data rate clock generating circuit 51 is configured to count the frequency divided clock S51 according to the oversampling rate k. As shown in FIG. 6, a wave chart (c) represents an oversampling counter value.
In the conventional clock generating circuit 200, the oversampling rate k is set to 10 (k=10). Accordingly, the oversampling counter value is in a range between 0 and 9. As shown in FIG. 6, a wave chart (d) represents the data rate clock S53 output as the frequency divided clock of the conventional clock generating circuit 200 and obtained through dividing the frequency of the frequency divided clock S51 according to the oversampling counter value.
Further, Patent Reference has disclosed a conventional clock frequency division method. In the conventional clock frequency division method disclosed in Patent Reference, an input clock pulse is masked at a specific timing, so that the input clock pulse thus masked is substantially delayed. Accordingly, a number of the clock pulse to be divided is adjusted, so that an average frequency of a divided clock becomes closer to an ideal clock frequency.
Patent Reference: Japanese Patent Publication No. 2010-087820
In the conventional clock generating circuit 200 described above, when the data rate is not divisible with the frequency division integer number (N), the frequency of the divided clock is shifted from the data rate. An example of the case will be explained below.
First, the frequency division integer number (N) is given by the following equation (1).N=round{f0/(D*k)}  (1)where f0 represents the frequency of the master clock (that is, the clock before the frequency division as the base for generating the data rate clock); D represents the data clock; and k represents the oversampling rate. In the equation (1), “round” is a function of obtaining a quotient of division and rounding a result of the division.
Further, the frequency of the data clock rate fD after the frequency division is given by the following equation (2) using the frequency division integer number (N) calculated with the equation (1).fD=f0/(N*k)  (2)
It is assumed that the frequency of the master clock f0 is 26 MHz (f0=26); the data clock D is 2.4 kbps (D=2.4); and the oversampling rate k is 10 (k=10). According to the equation (1), the frequency division integer number (N) is calculated to be 1083 (N=1083). Accordingly, using the equation (2), the frequency of the data clock rate fD is obtained as 2.4007386 kHz (fD=2.4007386). As a result, the frequency of the data clock rate fD is shifted from the data rate (2.4 kbps) by 308 ppm.
There may be a case that the shift of the data rate clock (a data rate deviation) from the data rate with the frequency fD is regulated according to standard specification and the like (for example, 100 ppm). If it's the case, when the data rate deviation is large, it may not be able to meet the standard specification.
In order to reduce the data rate deviation, it may be configured such that the frequency of the master clock is adjusted. However, when the frequency of the master clock is adjusted, the master clock no longer has a common frequency. Accordingly, it is difficult to reduce a cost of the master clock source (for example, a cost of an oscillation element), thereby increasing a cost of the communication system.
As another approach for reducing the data rate deviation, it may be configured such that a PLL (Phase Locked Loop) is adopted. When the PLL is used, it is possible to generate the master clock with the frequency integer number times of the data rate. With the approach, even when the integer number frequency division method is used, it is possible to generate the data rate clock with a minimum data rate deviation. However, when the PLL is used, it is difficult to reduce power consumption of the communication system.
In the clock frequency division method described in Patent Reference, an average frequency obtained through observing the output clock with the divided frequency over a specific period of time may be close to the data rate. However, individual clock wave forms still include pluses with a long time span and pluses with a short time span. Accordingly, in principle, the wave form of the output clock has a temporal fluctuation (so-called jitter).
In view of the problems of the conventional semiconductor device described above, an object of the present invention is to provide a method of generating a clock and a semiconductor device capable of generating a clock with a lower cost configuration and lower power consumption. Further, it is possible to minimize a data rate deviation from a target frequency and a temporal fluctuation.
Further objects and advantages of the invention will be apparent from the following description of the invention.